The present invention relates to a semiconductor integrated circuit device and a manufacturing method thereof and more specifically to a technique suitably applied to a semiconductor integrated circuit device having DRAMs (dynamic random access memories).
Recently developed large-capacity DRAMs employ a stack structure in which an information storage capacitive device or a capacitor is arranged over a memory cell selection MISFET to make up for reductions in the storage charge of the capacitor caused by miniaturization of memory cells.
Of the stack configuration memory cells, a memory cell of a capacitor-over-bitline (COB) structure in which a capacitor is located over the bit line has the advantages that the process burden in forming capacitors can be minimized because a stepped geometry of an underlying material of the storage node is planarized by the bit line and that a high signal-to-noise (S/N) ratio can be obtained because the bit line is shielded by the capacitor.
The COB structure memory cell may, for example, have a construction in which a first conductive film (polysilicon film or polycide film) deposited over the main surface of the semiconductor substrate is used to form a gate electrode of the memory cell selection MISFET and a first word line; in which a second conductive film (polysilicon film or polycide film) deposited over the first conductive film is used to form a bit line; in which a third conductive film (polysilicon film) deposited over the second conductive film is used to form a storage node of the capacitor; in which a fourth conductive film (polysilicon film) deposited over the third conductive film is used to form a plate electrode of the capacitor; and in which a fifth conductive film (Al alloy film or tungsten film) deposited over the fourth conductive film is used to form interconnects such as a second word line and a common source line. In this case, a BPSG (borophospho silicate glass) film is used as an insulation film between the fourth and fifth conductive films and a planarization processing such as reflow is performed to prevent possible breaks of interconnections formed of the fifth conductive film.